As a core device in PIC (Power Integrated Circuit), a power LDMOSFET (Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor) has the advantages of easy integration, low drive power and negative temperature coefficient, and has been developing for many years in the direction of high breakdown Voltage (BV) and lower specific On-Resistance (RON,sp). The higher breakdown Voltage BV requires that the device has a longer drift region length and a lower drift region doping concentration, which leads to a higher specific On-Resistance RON,sp. The contradiction between the breakdown Voltage BV and the specific On-Resistance Ro N, is the problem of “Silicon Limit” in the industry.
In order to alleviate this contradiction, and ensure the device has high breakdown Voltage BV and low specific On-Resistance RON,sp, the researcher introduces the dielectric trench in the LDMOS lateral drift region. The dielectric trench can withstand most lateral pressure and shorten the lateral dimension of the device, and greatly reduce the area of the chip. However, the traditional dielectric trench LDMOS still has a large specific On-Resistance RON,sp, which could not further relieve the contradiction between the breakdown Voltage BV and the specific On-Resistance RON,sp.